1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit and, more particularly, to a data I/O line control circuit and a semiconductor integrated circuit having the same.
2. Related Art
Referring to FIG. 1, a conventional semiconductor integrated circuit includes a memory cell 110, a sense amplifier 120 to sense and amplify data from the memory cell 110, a column select transistor 130 to transfer the data loaded on a pair of bit lines BL and BLB to a pair of local I/O lines LIO and LIOB, an I/O switching unit 140 to transfer the data loaded on the pair of local I/O lines LIO and LIOB to a pair of middle I/O lines MIO and MIOB, and a data sense amplifier 150 to transfer the data loaded on the pair of middle I/O lines MIO and MIOB to a pair of global I/O lines GIO and GIOB.
One word line WL1 of a plurality of word lines in a bank is activated by an active command. Data which are stored in a cell (FIG. 1 illustrates one of a plurality of cells in the bank) to be connected to the word line WL1 are loaded on the pair of the bit lines BL and BLB through a charge sharing operation and thereafter the sense amplifier 120 senses and amplifies the loaded data on the pair of the bit lines BL and BLB. The data loaded on the pair of the bit lines BL and BLB, which is associated with a corresponding column address, of a plurality of bit line pairs connected to the word line WL1 are outputted based on a read command. Subsequently, a column select signal (YS) is activated and the data loaded on the pair of the bit lines BL and BLB are transferred to the pair of the local I/O lines LIO and LIOB. The data loaded on the pair of the local I/O lines LIO and LIOB are transferred to the pair of the middle I/O lines MIO and MIOB, and the data loaded on the pair of the middle I/O lines MIO and MIOB are inputted into the data bus sense amplifier 150 for the sense amplifying operation.
According to the conventional memory device, when the column select signal (YS) is activated, the charge sharing operations are conducted between the pairs of the local I/O lines LIO and LIOB, the middle I/O lines MIO and MIOB and the bit lines BL and BLB. When the potential levels of the local I/O lines LIO and LIOB, the middle I/O lines MIO and MIOB and the bit lines BL and BLB are in a core voltage Vcore (at this time, the bar lines LIOB, MIOB and BLB of the local I/O line LIO, the middle I/O line MIO and the bit line BL are in a ground voltage level), there is no problem. However, when the potential levels of the local I/O line LIO and the middle I/O line MIO are in the core voltage Vcore and the potential level of the bit line BL is in the ground voltage level and when the charges flow into the bit line BL from the local and middle I/O lines LIO and MIO, the potential level of the bit line BL is bounced, that is, a voltage bouncing is caused on the bit line BL.
Referring to FIG. 2, which is a wave form diagram of the semiconductor memory device of FIG. 1, at an active mode, the potential level of the pair of the bit lines BL and BLB is amplified by the sense amplifier 120 and then the bit lines BL and BLB are respectively amplified to the core voltage level and the ground voltage level from a starting voltage level of the precharge voltage level. The wave form “S1” is taken by a normal operation of the pair of the bit lines BL and BLB. Referring to the wave form of S1, during a section in which the column select signal (YS) is activated, the potential level of the bit line BL rises from the ground voltage level and drops to the ground voltage level due to an influence of the potential level of the local I/O line LIO and the middle I/O line MIO. This voltage bouncing of the bit lines does not cause a problem because the normal wave form of the potential level is obtained by a latch operation of the sense amplifier 120; however, in some cases, when such a voltage bouncing is abnormally big, an abnormal voltage bouncing (A in FIG. 2), in which the potential levels of the bit lines BL and BLB are changed as shown in the wave form “S2”, may be caused because of the instant charge flowing from the local I/O line and the middle I/O line MIO.